1. Field of the Invention
This invention relates to integrated-circuit packaging technology, and more particularly, to a method of encapsulating a substrate-based package assembly without causing mold flash over exposed package surfaces.
2. Description of Related Art
Encapsulation process is an important step in integrated-circuit packaging technology, by which an epoxy-molded compound (EMC), or called an encapsulation body, is formed to encapsulate the packaged semiconductor chip for the purpose of protecting the packaged semiconductor chip against outside moisture, contamination, and damage.
One problem to the encapsulation of a substrate-based package, however, is that the encapsulation material would easily flash to the exposed package surfaces where electrical contacts are provided, thus adversely degrading the electrical coupling of those electrical contacts to external circuitry. This problem is illustratively depicted in the following with reference to FIGS. 1A-1C, FIGS. 2A-2B, FIGS. 3A-3B, and FIGS. 4A-4C, respectively for four different types of substrate-based packages.
Case 1: Wire-Bonded Single-Chip Package
FIGS. 1A-1C are schematic sectional diagrams used to depict a conventional encapsulation method for a wire-bonded single-chip package.
Referring first to FIG. 1A, this wire-bonded single-chip package assembly includes: (a) a substrate 100 having a front surface 100a and a back surface 100b; (b) a semiconductor chip 110 mounted on the front surface 100a of the substrate 100; (c) a first electrically-insulative layer 121 serving as a top solder mask (S/M) over the front surface 100a of the substrate 100; (d) a second electrically-insulative layer 122 serving as a bottom solder mask over the back surface 100b of the substrate 100; and (e) a plurality of electrical contacts 130 provided on the back surface 100b of the substrate 100 and electrically isolated from each other by the second electrically-insulative layer 122.
The foregoing semi-finished package assembly is to be encapsulated through the use of a molding tool 140 composed of a bottom mold 141 having a flat top surface 141a and an upper mold 142 having a predefined cavity 142a. 
Referring to FIG. 1B, during encapsulation process, the semi-finished package assembly shown in FIG. 1A is fixed in the molding tool 140 in such a manner that the second electrically-insulative layer 122 on the back surface 100b of the substrate 100 is abutted on the flat top surface 141a of the bottom mold 141. Then, an encapsulation material, such as epoxy resin, is injected into the mold cavity 142a (through the path indicated by the arrow M in FIG. 1B) to thereby form an encapsulation body 150 to encapsulate the semiconductor chip 110 and the substrate 100.
Undesirably, however, since it would be highly difficult to make the second electrically-insulative layer 122 come into absolutely airtight abutment on the flat top surface 141a of the bottom mold 141, a seam (indicated by the letter S in FIG. 1B) would exist between the second electrically-insulative layer 122 and the bottom mold 141, which would allow a small amount of the encapsulation material to flash over the bottom surface of the second electrically-insulative layer 122.
Referring further to FIG. 1C, as the encapsulation process is completed, the encapsulated package assembly is taken out from the molding tool 140. As a consequence of mold flash, a mass of mold flash 150a would be undesirably left over the exposed bottom surface of the second electrically-insulative layer 122 and even over the electrical contacts 130. The mold flash 150a would undesirably make the resulted package unit spoiled in its outer appearance and make the electrical contacts 130 unable to be reliably electrically coupled to external circuitry.
One solution to the foregoing problem of mold flash is to perform a de-flash process through the use of sanding means or laser means to remove the mold flash 150a. One drawback to this solution, however, is that it would easily cause damage to the substrate surfaces, thus spoiling the outer appearance of the resulted package unit.
Case 2: Wire-Bonded Stacked-Dual-Chip Package
FIGS. 2A-2B are schematic sectional diagrams used to depict a conventional encapsulation method for a wire-bonded stacked-dual-chip package which also suffers from the problem of mold flash.
As shown in FIG. 2A, this wire-bonded stacked-dual-chip package assembly includes: (a) a substrate 200 having a front surface 200a and a back surface 200b; (b) a pair of stacked semiconductor chips 211, 212 mounted on the front surface 200a of the substrate 200; and (c) an electrically-insulative layer 220 serving as a solder mask (S/M) over the back surface 200b of the substrate 200.
In encapsulation process, the same molding tool as the one shown in FIGS. 1A-1B can be used to encapsulate the foregoing semi-finished package assembly, so detailed description thereof will not be repeated herein.
As further shown in FIG. 2B, as the encapsulation process is completed, a mass of mold flash 250a would be undesirably left over the edge of the exposed back surface of the electrically-insulative layer 220.
Case 3: Flip-Chip Package
FIGS. 3A-3B are schematic sectional diagrams used to depict a conventional encapsulation method for a flip-chip package which also suffers from the problem of mold flash.
As shown in FIG. 3A, this flip-chip package assembly includes: (a) a substrate 300 having a front surface 300a and a back surface 300b; (b) a semiconductor chip 310 mounted in an upside-down (i.e., flip chip) manner on the front surface 300a of the substrate 300; and (c) an electrically-insulative layer 320 serving as a solder mask (S/M) over the back surface 300b of the substrate 300.
In encapsulation process, the same molding tool as the one shown in FIGS. 1A-1B can be used to encapsulate the foregoing semi-finished package assembly, so detailed description thereof will not be repeated herein.
As further shown in FIG. 3B, after the encapsulation process is completed, a mass of mold flash 350a would be undesirably left over the edge of the exposed back surface of the electrically-insulative layer 320.
In the foregoing three cases, the problem of mold flash occurs on the exposed back surface of the electrically-insulative layer coated over the back surface of the substrate. However, the problem of mold flash may also occur on the front surface of the substrate, as in the case of a BGA package depicted in the following with reference to FIGS. 4A-4C.
Case 4: BGA-Package
FIGS. 4A-4C are schematic sectional diagrams used to depict a conventional encapsulation method for a BGA (all Grid Array) package which also suffers from the problem of mold flash.
Referring first to FIG. 4A, this BGA package assembly includes: (a) a substrate 400 having a front surface 400a and a back surface 400b; (b) a semiconductor chip 410 mounted on the front surface 400a of the substrate 400; (c) a first electrically-insulative layer 421 serving as a top solder mask (S/M) over the front surface 400a of the substrate 400; (d) a second electrically-insulative layer 422 serving as a bottom solder mask (S/M) over the back surface 400b of the substrate 400; and (e) a plurality of solder-ball pads 430 provided on the back surface 400b of the substrate 400 and electrically isolated from each other by the second electrically-insulative layer 422.
The foregoing semi-finished BGA package assembly is to be encapsulated through the use of a molding tool 440 composed of a bottom mold 441 having a flat top surface 441a and an upper mold 442 having a predefined cavity 442a and a flat bottom surface 442b. 
Referring to FIG. 4B, during encapsulation process, the semi-finished BGA package assembly shown in FIG. 4A is fixed between the bottom mold 441 and the upper mold 442, in such a manner that the second electrically-insulative layer 422 on the back surface 400b of the substrate 400 is rested on the fiat top surface 441a of the bottom mold 441, while the semiconductor chip 410 is entirely accommodated within the mold cavity 442a. Then, an encapsulation material, such as epoxy resin, is injected into the mold cavity 442a (through the path indicated by the arrow M in FIG. 4B) to thereby form an encapsulation body 450 to encapsulate the semiconductor chip 410 and the substrate 400.
Undesirably, however, since it would be highly difficult to make the flat bottom surface 442b of the upper mold 442 come into absolutely airtight abutment on the first electrically-insulative layer 421, a small amount of the encapsulation material would flash through the seam indicated by S in FIG. 4B to the top surface of the first electrically-insulative layer 421.
Referring further to FIG. 4C, as the encapsulation process is completed, the encapsulated package assembly is taken out from the molding tool 440. As a consequence of mold flash, a mass of mold flash 450a would be undesirably left over the exposed top surface of the first electrically-insulative layer 421, thus undesirably spoiling the outer appearance of the resulted package unit.
Related patents, include, for example, the U.S. Pat. No. 6,040,622, which discloses a substrate-based package configuration for the fabrication of a multi-media card (MMC). In the utilization of this patented technology, however, mold flash is still a problem.
It is therefore an objective of this invention to provide a method for encapsulating a substrate-based package assembly without causing mold flash over exposed package surfaces.
In accordance with the foregoing and other objectives, a new encapsulation method for substrate-based package assembly is proposed.
Broadly recited, the encapsulation method of the invention comprises the following steps: (1) preparing a molding tool having a predefined cavity; (2) forming a cutaway portion in the electrically-insulative layer along a seam line between the electrically-insulative layer and the solid part of the molding tool that would exist between the electrically-insulative layer and the solid part of the molding tool when the substrate-based package assembly is fixed in position in the molding tool, the cutaway portion being dimensioned to a predetermined height and a predetermined width; (3) fixing the substrate-based package assembly in the cavity of the molding tool, with the cutaway portion defining a constricted flow passage between the substrate and the solid part of the molding tool and (4) injecting an encapsulation material into the cavity of the molding tool for the purpose of molding an encapsulation body for encapsulating the substrate-based package assembly, wherein the flow of the encapsulation material within the constricted flow passage is retarded in speed and increased in viscosity.
During the encapsulation process, the cutaway portion defines a constricted flow passage to the injected encapsulation material; and consequently, when the encapsulation material flows into this constricted flow passage, it would more quickly absorb the heat in the solid part of the molding tool, thereby increasing its viscosity and retarding its flow speed. As a result, the encapsulation material would be less likely to further flow into the seam between the electrically-insulative layer and the solid part of the molding tool, thus preventing mold flash over the exposed surface of the electrically-insulative layer.